COMPUTATIONAL RESEARCH in BOSTON and BEYOND (CRIBB)

New architectures require thoughtful testing to explore the performance potential of the processor. Here the HPEC Challenge Benchmarks are used to explore the Cell processor to understand the realistic performance as well as how that performance can be attained. More specifically, for the time domain FIR benchmark, we find that a significant fraction (88%) of the peak performance can be achieved (as expected). However, this performance does come at significant coding cost.

This work is sponsored by AFRL under Air Force contract FA8721-050C-0002. Opinions, interpretations, conclusions and recommendations are those of the author and not necessarily endorse by the United States Government.