COMPUTATIONAL RESEARCH in BOSTON and BEYOND (CRIBB)

Conventional computer architectures poorly handle cache-unfriendly applications. The problem stems in part from the irregular memory-access patterns exhibited by these applications and in how remote memory accesses are handled. Today's data intensive applications, such as sparse-matrix linear algebra and graph analytics, do not exhibit the same locality traits as compute-intensive applications, resulting in the latency of individual memory accesses overwhelming the advantages of deeply pipelined fast cores.

The "weak-locality" that data-intensive applications do exhibit where irregular accesses occur within a large memory region of several gigabytes can be exploited by an innovative architectural approach. The Emu Mirgratory Memory-Side Processing architecture provides a highly efficient, fine-grained memory system and migrating threads that move the thread state, as new memory locations are accessed, without explicit program directives. The "put-only" communication model dramatically reduces thread latency and total network bandwidth load as return trips and cache coherency are eliminated.

This talk covers: how the architecture delivers orders of magnitude reduction in data movement, inter-process communication and energy requirements; the familiar programming model selected for the architecture which makes it accessible to programmers and data scientists; real-world results of graph analytics and sparse algorithms that validate the architectural vision