Date Mar. 6, 2009
Speaker Mirian Leeser (Northeastern University)
Topic Vforce: Aiding the Productivity and Portability in Reconfigurable Supercomputer Applications via Runtime Hardware Binding

Recently there has been an explosion of new computer architectures that combine multiple CPUs with Special Purpose Processors (SPPs). Examples of SPPs include Field Programmable Gate Arrays (FPGAs), Graphics Processing Units (GPUs) and the Cell Broadband Engine. Powerful multicomputer platforms that combine SPPs and CPUs in a single hardware architecture promise tremendous performance benefits. Applications that can run on any of these platforms, deliver performance and be easily ported to other platforms are highly desirable. Traditional programming practices, however, intertwine application code with hardware specific code such that porting entails a significant rewrite of the application and reuse of code is difficult.

VSIPL++ for Reconfigurable Computing (Vforce) is a middleware framework that extends VSIPL++ (a C++ extension of the Vector, Signal, and Image Processing Library) to include support for special purpose processors (SPPs). Vforce is an extensible framework that allows the same application code to run on different heterogeneous computing platforms. Vforce offers application-level portability, framework-level extensibility to new hardware, and system-level run time resource management. In particular, Vforce supports very late binding of the application to a specific hardware platform such that binding does not occur until run time.

In this talk, I will give a brief introduction to VSIPL++ and to some commercially available heterogeneous multicomputers. Then I will present the Vforce framework and explain how it supports the three goals of performance, productivity and portability. I will present our experience using Vforce on different hardware platforms (including those with FPGAs and those with GPUs) as well as different applications.

Biography Miriam Leeser is a Professor at Northeastern University, Department of Electrical and Computer Engineering. She received her BS degree in Electrical Engineering from Cornell University, and Diploma and Ph.D. Degrees in Computer Science from Cambridge University in England. After completion of her Ph.D., she joined the faculty of Cornell University, Department of Electrical Engineering as an Assistant Professor. In January, 1996 she joined the faculty of Northeastern University, where she is head of the Reconfigurable Computing Laboratory and a member of the Computer Engineering research group and the Center for Communications and Digital Signal Processing. In 1992 she received an NSF Young Investigator Award to conduct research into Floating Point Arithmetic. Her research interests include hardware description languages, programming paradigms for many core computers, computer arithmetic and reconfigurable computing for signal and image processing applications. She is a senior member of the IEEE and of the ACM.



We thank the generous support of MIT IS&T, CSAIL, and the Department of Mathematics for their support of this series.

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